Field of the Invention
This invention relates to phase-locked loops and more particularly to locking a feedback signal to an input signal.
Description of the Related Art
FIG. 1 shows a typical phase-locked loop (PLL) 100 in which an input clock signal 103 is compared to a feedback signal 105 in phase frequency detector (PFD) and charge pump 107. The PFD supplies the phase/frequency information containing the difference between the input clock signal 103 and the feedback signal 105 to the charge pump, which in turn supplies the loop filter 111. The loop filter controls the voltage controlled oscillator (VCO) 115, which supplies the output clock signal 117. A feedback divider 119 divides the output clock signal 117 based on a divide control signal 121 and supplies the feedback signal 105. The VCO 115 is controlled to lock the feedback signal 105 to the phase and frequency of the input clock signal 103 based on the output of the PFD and charge pump 107.
The locking time for the PLL can be very large for low frequency inputs. Typically, the loop bandwidth of the PLL is less than the frequency of the input clock signal. For example, for an input clock signal of one pulse per second (1 PPS) the loop bandwidth may be in the milliHz range. For such a loop bandwidth, the locking time can be hours or days when the difference between the input clock signal and the feedback signal at startup may be up to, e.g., ±a half second.
Such large differences at startup require circuits that can handle representing the large differences. Thus, such circuits have large full scale requirements, where full scale corresponds to the expected maximum difference between the input signals. Phase frequency detector (PFD) offsets are large when designed for a wide range of inputs due to large full scale requirements. The large full scale requirements result in the possibility that the different circuit paths for each input have circuit differences due to process variations resulting in offsets present between the two paths. For example, the different paths may have different resistance and capacitances due to process variations that can increase under certain temperature conditions. On the other hand, if the full scale requirements are not met, clipping results in a non-linear response in the PFD. To avoid clipping however, meeting large full scale requirements can result in large offsets and thus inaccuracy in the measurement of the differences between the two input signals to the PFD.
Some PLLs have multiple input clocks that can be selected so that the PLL can switch between input clock signals when one of the input clocks fails or when a switch from one reference frequency to another reference frequency is desired. When a loss of signal for one of the input clocks occurs resulting in a loss of lock (LOL) indication, or a manual switch occurs, conventional switching approaches require long digital capture and computation cycles to evaluate the new clock signal and adjust the PLL output. That is, the new input clock is observed for a long time to determine how the new input clock compares to the old input clock and in the meantime, the oscillator output is typically frozen as the new input clock signal is evaluated. That long evaluation time can be particularly true for a low frequency input clock signal. Waiting to lock to the new input signal can be detrimental to the system as errors in the currently frozen output clock signal from the PLL may be present until the PLL is able to lock to the new input clock signal.
In addition, very low bandwidth filters, e.g., in the milliHz range, may be disrupted by large phase/frequency corrections. For example, large phase/frequency corrections expose low latency IIR filters to instability at their full scale.
Accordingly, improvements in PLLs is desirable to address at least some of the issues described above.